A 1.25GHz 0.35pm Monolithic CMOS PLL Clock Generator for Data Communications
نویسندگان
چکیده
A 1.25GHz monolithic CMOS PLL clock synthesis unit was designed for data communications. The monolithic PLL consists of a ring oscillator, divider, phase/frequency detector, charge pump and on-chip loop filter. The voltage controlled oscillator incorporates a quadrature output ring structure with sub-feedback loop embedded to speed up the circuit. The design accommodates process, supply voltage and temperature variations. The PLL has been fabricated in a 0.35pm CMOS process, occupies an active area of 1 mm2, and consumes 100 mW power at 3.3V.
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